Interfacing Networks-on-Chip

Wireless communication is becoming more and more important in today’s world. We rely on radio transmission for audio/video broadcasts, telecommunication, satellite navigation, security systems and many wireless sensor devices. These communication systems use reserved parts of the frequency spectrum, to ensure low interference between transmitters and receivers of different communication systems. Since spectrum is scarce, many advanced wireless standards have been proposed to efficiently use parts of the spectrum, by applying (often complex) digital processing to the signal to be transmitted. Another approach to efficiently use the spectrum is by applying spatial filtering, which can be done by using multiple antennas that are used one at a time (spatial diversity), or by using multiple antennas coherently (in a phased array). An important aspect of wireless communication is battery lifetime. However, the digital processing algorithms, used to increase the spectrum utilization, require complex operations to be performed at high speeds by the hardware platform. Therefore, the ever increasing complexity of such algorithms poses tough requirements for next-generation hardware platforms. Instead of realizing a single complex processor with high transistor count, current single-chip architectures are based on multiple, less complex processors that work in parallel. They share a single memory space, which is accessible via a shared communication infrastructure. For small numbers of processors, a shared bus can be used efficiently and implementation costs are low. However, future architectures will consist of tens to hundreds of processors, which will be limited in performance when they have to share the bandwidth provided by a bus interconnect structure. A Multi-processor System-on-Chip (MPSoC) with a Network-on-Chip (NoC) interconnect solves the problem of bus sharing. Each processor is connected to a local router, which on its turn is connected to a fixed number of other routers. Since the number of connections per router is independent of the number of routers and processors in the network, such a system can be scaled without losing interconnect efficiency. Processors can communicate via the NoC by using Virtual Channels (VCs), which are created by configuring the routers on the path from one processor to another, such that data received on the input port is forwarded to the correct output port. The arbitration protocol used by the routers is designed such that a minimum bandwidth guarantee and a maximum latency guarantee can be given for VCs mapped on the NoC. This thesis presents the design and analysis of the Hydra Network Interface